This invention relates to the field of digital circuits. More precisely, this invention relates to the field of interconnection of processing blocks.
A digital circuit comprises combinational units, logic gates, sequential units, memorizing units, etc.
In a circuit comprising these units, at least one clock is responsible for providing a time reference to these units, such a circuit is considered to be synchronous.
In complex circuits comprising a plurality of units, it is frequent to observe that each of the plurality of units operates at a different pace. In such a situation, it is important to adequately control each clock signal provided to each of the plurality of units.
Usually, for instance, phase lock loop (PLL) devices are used to insure proper phase synchronization, if needed.
It will be appreciated that it may be very difficult to provide a clocking scheme to a plurality of processing units, each having its clock own value when two clock values are relatively prime, i.e. when a division of one clock value by the other clock value leads to a large number.
In the case of a Field Programmable Gate Array (FPGA) embodiment of a circuit, phase lock loop devices are inexistents. It will further be appreciated by someone skilled in the art that the number of available clock buffers as well as the number of clock signals that can be provided in a single field programmable gate array is limited with some design tools such as Synthesis.
Furthermore, in the case of a sequence of serially connected processing units, it will be appreciated that prior art clocking embodiments do not allow an easy change of one of the serially connected processing units.
It is therefore an object of the present invention to overcome the above-mentioned drawbacks.
It is an object of the invention to provide a method for performing a synchronous clocking of a plurality of processing units.
It is another object of the invention to provide an apparatus for performing a synchronous clocking of a plurality of processing units.
Yet another object of the invention is to provide a clocking apparatus to a plurality of processing units that will enable a user to change at least one of the processing units with another one having a different clocking speed.
According to a first object of the invention, there is provided a method for performing a synchronous clocking of a first clock-dependant processing unit connected to a second clock-dependant processing unit, the method comprising the steps of providing a first clock-dependant processing unit, receiving a data signal to process and providing a first data signal, providing a second clock-dependant processing unit, receiving the first data and providing a second data signal, providing a main clock signal to each of the two clock-dependant processing units and providing an interblock synchronization signal to one of said clock-dependant processing unit by another one of said clock-dependant processing units, having a processing speed substantially lower than the one, when the first clock-dependant processing unit is ready to provide the first data signal to the second clock-dependant processing unit, wherein the providing of an interblock synchronization signal when the first clock-dependant processing unit is ready to provide the first data signal to the second clock-dependant processing unit enables a synchronous clocking of the first clock-dependant processing unit connected to the second clock-dependant processing unit.
According to another aspect of the invention, there is provided an apparatus for performing a synchronous clocking of a first clock-dependant processing unit connected to a second clock-dependant processing unit, the apparatus comprising a first clock-dependant processing unit receiving a data signal to process and providing a first data signal, a second clock-dependant processing unit receiving the first data signal and providing a second data signal, the second clock-dependant processing unit being connected to the first processing unit using an interblock synchronization connection and a main clock signal providing unit providing a main clock signal to each of the two clock-dependant processing units, wherein one of the clock-dependant processing unit provides an interblock synchronization signal to another clock-dependant processing unit using the interblock synchronization connection when the first clock-dependant processing unit is ready to provide the first data signal to the second clock-dependant processing unit.